The speed and reliability performance parameters of state-of-the art semiconductor integrated circuit (IC) chips are mostly governed by the on-chip interconnects. Advanced semiconductor IC chips employ multi-level on-chip interconnects usually comprising aluminum (usually an alloy of aluminum comprising approximately 0.5% to 2% copper for improved electromigration reliability lifetime) metal lines, aluminum (again typically doped with copper) or tungsten plugs (for inter-level/inter-metal contact/via holes), and silicon dioxide (or fluorinated silicon dioxide SiO.sub.x F.sub.y) or a combination of silicon dioxide with an organic low-permittivity (low-k) dielectric used as inter-metal and inter-level dielectrics. The speed performance of advanced semiconductor IC chips such as high-end microprocessors and digital signal processors (DSP) fabricated using 0.25 .mu.m complementary metal-oxide-semiconductor (CMOS) technologies and beyond is limited by the interconnect signal propagation delays. The signal propagation delay for advanced interconnects is limited by the parasitic resistive, capacitive, and inductive elements. These include the interconnect metal "RC" delays, capacitive cross-talks or cross-talk noise between adjacent metal lines (due to voltage pulses), as well as inductive noise and cross-talks (due to voltage pulses).
As the device dimensions are scaled down, the metal interconnect line widths and pitches are also scaled down, accordingly. The maximum density (areal density) of metal interconnect lines on each interconnect level is limited by the minimum electrical conductivity requirements of the metal lines as well as the upper limits on the maximum allowable signal cross-talks. As the density of the metal interconnect lines on each interconnect level increases, the adjacent metal lines are placed closer to each other and the widths of the metal lines is also reduced. As the minimum feature size of the semiconductor (e.g., silicon CMOS) IC technologies is reduced to 0.25 .mu.m and beyond, the "RC" propagation delays and the capacitive cross-talk noise have a significant impact on the speed performance of the IC chips, such as in high-end microprocessor and digital signal processor (DSP) chips. These problems place serious constraints on the minimum width (and thickness) of the metal lines and the minimum metallization layout pitches (or the minimum inter-line spacings), particularly on the interconnect levels which contain the long-range global interconnect lines (for instance, for signal or clock distribution) and/or power distribution.
The interconnect design rule constraints caused by the IC chip speed performance (and electromigration reliability lifetime) requirements result in an increase in the number of interconnect levels, particularly for complex logic chips such as high-end/high-speed microprocessors and digital signal processors. For instance, state-of-the-art CMOS logic technologies with minimum feature size of 0.20 to 0.25 .mu.m may utilize as many as six or more levels of metal interconnects. Each additional level of metal interconnect adds significantly to the overall process flow complexity and chip manufacturing cost. This is due to both increased number of fabrication process steps in the process flow and the manufacturing yield reduction associated with a more complex and lengthy process flow.
Another limitation associating with existing interconnect structures arises because metal resistivity significantly contributes to the chip speed constraints and even the overall manufacture cost. The use of a higher conductivity metal such as copper instead of aluminum, since the bulk resistivity of copper is approximately 1.78 .mu..OMEGA..cndot.cm versus approximately 2.7 .mu..OMEGA..cndot.cm for aluminum, results in a significant reduction of the interconnect "RC" propagation delay for a given metal interconnect width and thickness. On the other hand, for a given interconnect line parasitic resistance, a higher metal conductivity (e.g., Cu instead of Al) allows the use of thinner metal lines on each interconnect level for a given metal line width. This, in turn, enables closer spacings between the adjacent metal lines or equivalently, a higher areal density of metal interconnect lines on each level for a given distribution of intra-level capacitive signal cross-talks.
The higher interconnect line densities on various interconnect levels enable a reduction in the number of required interconnect levels for a given chip speed performance. This results in reduced process complexity and cost. Alternatively, a higher conductivity conductor (e.g., copper instead of Al) can be used to not only reduce the process complexity and cost through reduction of the number of interconnect levels, but also to improve the chip speed performance. This can be done by both reducing the metal line resistance, increasing the interconnect metal line resistance, and increasing the interconnect metal line areal density.
For example, in an advanced 0.18 .mu.m microprocessor logic chip, for a given maximum speed or clock frequency (e.g., an approximately 600-MHz microprocessor), comprising eight levels of Al metal interconnects, replacing Al with Cu accomplishes a number of desireable results. For instance, it is possible to reduce the process complexity and chip fabrication cost by, perhaps, approximately 30% while achieving the same speed performance of approximately 600 MHz. This can be achieved by reducing the number of interconnect levels from 8 to 6 and also due to the reduced number of process steps per level for copper interconnect compared to aluminum interconnect. It is also be possible to reduce the process complexity and chip fabrication cost by, perhaps, approximately 15-20%, while also improving the chip speed performance by, for instance, approximately 10% to approximately 660 MHz. For example, this may be achieved by reducing the number of metal interconnect levels from 8 to 7 and also reducing the resistance of the metal lines at the same time.
Besides the interconnect metal, the inter-metal/inter-level dielectric layers (IMD and ILD layers) also have a significant impact on the IC chip performance speed as well as manufacturing cost. The dielectric constant (i.e. relative dielectric constants with respect to free space) of the IMD/ILD material layers impacts not only the "RC" propagation delays but also the intra-level and inter-level capacitive cross-talks.
The mainstream ILD/IMD materials in silicon chip manufacturing are silicon dioxide (SiO.sub.2) and/or derivatives of silicon dioxide (such as fluorinated silicon dioxide: SiO.sub.x F.sub.y) with k values in the range of 3.2 to over 4.0. There has been a significant amount of materials research on low-k dielectrics. The lowest practical k values to date have been reported for some spin-on organic dielectrics and porous aerogels/xerogels. The practical low-k dielectrics developed to date have k values in the range of 2.0 to 3.2. These low-k dielectrics, however, complicate the back-end interconnect process integration due to their inferior thermal stability as well as their electrical, mechanical and thermal conductivity properties compared to silicon dioxide.
FIG. 1 illustrates a side view of an interconnect structure 10 that includes a low-k organic ILD/IMD material layer 12 and trench 14. SiO.sub.2 layer 16 covers ILD/ILD substrate 12. Covering trench 14 and top SiO.sub.2 layer 16 is conformal SiO.sub.2 buffer layer 18. The formation of organic low-k dielectric layer 12 also complicate the single or dual damascene processes commonly used for fabrication of copper interconnects due to the difficulties associated with their incompatibility with chemical-mechanical polishing (or CMP) processes used for copper and barrier removal during the interconnect fabrication process. As a result, most organic low-k dielectrics employ a suitable hard mask layer such as silicon dioxide for single or dual-damascene interconnect fabrication processes in order to facilitate formation of dielectric trenches and via holes for the embedded (inlaid) metal (e.g., copper) lines.
The optimal integration of most organic low-k dielectrics requires deposition of a thin conformal layer of, for instance, silicon dioxide, such as SiO.sub.2 layer 18, followed by an anisotropic oxide etch process in order to cover the trench and via hold sidewalks with a thin layer of high-quality silicon dioxide dielectric, such as SiO.sub.2 layer 18. This prevents a direct contact between the low-k dielectric and the deposited glue/barrier layer and may improve the overall breakdown voltage and leakage characteristics of the composite ILD/IMD layers. This requirement adds to the complexity and fabrication cost of the IMD/ILD integration. Moreover, the effective relative dielectric constant of the composite IMD/ILD layers is somewhat higher than that of the low-k dielectric by itself. This is due to the requirements for the hard mask and sidewalk oxide coverage.
One attempt to provide a lowest possible relative permittivity or k value has been to use free space dielectric between interconnects. Free space provides the best possible dielectric since it provides k=1. This is a factor of approximately 4 times better than silicon dioxide and even a factor of 2 to 3 better than the best practical low-k dielectric materials. As a result, for a given metal conductivity and sheet resistance distribution, the free-space dielectric results in a significant reduction of the interconnect "RC" propagation delays and capacitive cross-talk noise.
The main challenges with the free-space dielectric IMD/ILD integration are the ability to remove heat from the multi-level interconnect structure and the ability to form a hermetically sealed chip packages protecting the multi-level interconnect structure and the active devices on the substrate.
The prior art multi-level interconnect structures (using either silicon dioxide or any solid ILD/IMD low-k material layer) typically require an effective glue/barrier layers. This is particularly critical for a high electrical conductivity material such as copper (or silver) since copper (or silver or gold) act as electrical trap centers in silicon and can severely degrade the transistor properties such as transconductance, junction leakage, standby power dissipation and reliability lifetime. Moreover, copper, as well as some other metallic elements such as gold and silver can cause severe degradation of the ILD/IMD layers adversely affecting their electrical leakage and breakdown properties. As a result, the prior art silicon chip interconnect structures and fabrication process flows employ conductive diffusion barrier layers (such as TiN, Ta, TaN, TiSiN, TaSiN, WN, WSiN, MoN, or MoSiN). The long-term chip reliability lifetime and chip manufacturing yield requirements place limits on the minimum thickness of the barrier material for such devices.
As the chip IC device dimension are scaled down, the width of the metal lines and also the dimensions or diameters of the via plugs are also reduced, whereas the thickness of the diffusion barrier layer is scaled down more slowly. Thus, with each successive technology generation, the barrier material thickness (and cross sectional area) becomes a larger fraction of the conductive interconnect lines. One example of this phenomenon can be examined in the case of dual-damascene copper interconnects. In IC chips with copper metallization, a larger fraction of the diameter of the conductive via plug is also consumed by the barrier material. For instance, for a damascene trench width of 0.20 .mu.m and a conformal diffusion barrier thickness of 250 .ANG. (deposited, for example, by a conformal chemical-vapor deposition or CVD process), the high-conductivity metal (e.g., copper with a resistivity of approximately 1.8 .mu..OMEGA..cndot.cm) only occupies a metal line width or a via plug diameter of only 0.15 .mu.m, due to the peripheral space occupied by the diffusion barrier layer. Since the typical diffusion barrier layers have much higher electrical resistivity values compared to the high-conductivity interconnect metals (e.g., in the range of approximately 150-250 .mu..OMEGA..cndot.cm for Ta and TaN diffusion barriers vs. approximately 1.8 .mu..OMEGA..cndot.cm for copper), the diffusion barrier layer degrades the overall interconnect metal line resistance, as well as via plug resistance values. For instance, FIG. 2 shows damascene dielectric trench structures 20 and 22 (e.g., for fabrication of embedded copper metal line) with a width W and height H.
In damascene dielectric trench structure 22 (FIG. 2b), trench 24 is filled entirely with the high conductivity metal line having electrical resistivity of .rho..sub.m. On the other hand, damascene trench structure 20 (FIG. 2a) includes barrier layer 26 (shown as a conformal layer) with a layer thickness t.sub.b and a material resistivity of .rho..sub.b in trench 28. The high conductivity metal line 28 occupies the remaining space surrounded by the barrier layer. Assuming .rho..sub.b &gt;&gt;.rho..sub.m, which is typically the case in practice, we can compare the total conductor line resistance per unit length for these two conditions:
R.sub.1 .DELTA. conductor line resistance per unit length without the barrier layer (FIG. 2b); PA1 R.sub.2 .DELTA. conductor line resistance per unit length with the barrier layer (FIG. 2a) ##EQU1## Since .rho..sub.b &gt;&gt;.rho..sub.m, the conclusion follows that R.sub.2b &gt;&gt;R.sub.2m and, as a result, ##EQU2## For instance, assume W=0.25 .mu.m, H=0.50 .mu.m, t.sub.b =250 .ANG. (0.025 .mu.m) , and Pm=2 .mu..OMEGA..cndot.cm: ##EQU3## As a result, in this example, the presence of the barrier layer has degraded the effective interconnect line resistance by over 30% which is a significant amount of interconnect conductor conductivity loss. PA1 R.sub.P2 .DELTA. effective via plug resistance with the barrier layer (FIG. 3a); and PA1 R.sub.P1 .DELTA. effective via plug resistance without the barrier layer (FIG. 3b).
Similarly, the barrier layer can also degrade the effective via plug resistance. For instance, FIG. 3 shows via plugs 30 and 32 connecting the metal lines between two adjacent interconnect levels. Via plug 30 (FIG. 3a) includes metal plug between metal lines 34 and 35 which is fully surrounded at the bottom and sidewalls by the barrier layer 36. Via plug 32 of FIG. 3b, on the other hand, shows an ideal situation without a barrier layer surrounding metal plug 32 (connecting metal lines 38 and 40).
Assume the via hole (cylindrical via hole) has a diameter of D and a height of H. We can also define the following parameters:
Also, assume that the via plug metal has a resistivity of .rho..sub.m (1.8 .mu..cndot.cm), which is preferably the same as that of the interconnect metal lines on levels N and N-1). Moreover, assume that the barrier layer is conformal, has a thickness of t.sub.b, and a resistivity of .rho..sub.b. Moreover, assume that .rho..sub.b &gt;&gt;.rho..sub.m. Let's calculate R.sub.P1 and R.sub.P2 for the two via plug structures of FIGS. 3a and 3b: ##EQU4## Since .rho.b&gt;&gt;.rho.m ##EQU5## Where Rc is the effective contact resistance at each interface between the barrier layer and either the via metal plug or the underlying metal line. As an example, assume D=0.25 .mu.m, H=0.75 .mu.m, t.sub.b =250 .ANG. (0.025 .mu.m), and P.sub.m =2 .mu..OMEGA..cndot.cm (.rho..sub.b &gt;&gt;.rho..sub.m). Assume that .rho..sub.b =200 .mu..OMEGA..cndot.m. R.sub.P1 and R.sub.P2 can be calculated as follows: ##EQU6## Thus, R.sub.P1 =0.305 .OMEGA. which is the plug resistance for the ideal case without the barrier layer. ##EQU7## Thus, R.sub.Pz =1.480+2Rc .OMEGA., which is the plug resistance for the via plug structure comprising the barrier layer.
It can be seen that even without including the contact resistance contribution 2Rc (due to the two barrier/metal it contact interfaces in each plug), the barrier layer results in a significant degradation of the overall via plug resistance. This effect, in turn results in the degradation of the chip speed due to the increased "RC" propagation delays in the interconnect structure.
In light of the above information, therefore, there is need for a semiconductor IC chip interconnect structure and a related fabrication process flow which can significantly reduce the parasitic resistive and capacitive elements, as well as the related "RC" propagation delays and interconnect capacitive cross-talks. Satisfying this need will enable much faster chip operations and/or lower chip power consumption.
Moreover, there is a need for an improved chip interconnect structure and related process flow which can enable a reduction of the total number of on-chip interconnect levels required for fabrication of high performance semiconductor IC chips. Satisfying this need results in a reduction in the chip fabrication process flow complexity, improving the manufacturing yield, and reducing the overall production costs.
There is the need for an interconnect structure and a related interconnect fabrication process flow which enable the use of a lowest possible dielectric permittivity for IMD/ILD applications.
There is a further need for an interconnect structure and related fabrication process flow that can eliminate the additional process complexities and fabrication cost associated with the integration of low-k dielectric materials by using free-space as the IMD/ILD layers. There is also a need for an advanced multi-level interconnect structure and a related fabrication process flow which enable efficient heat removal from the interconnect structure, and also allow formation of a fully hermetically sealed chip package.